U.S. Pat. No. 3,550,082 discloses a process for synchronizing a receiver with digitally transmitted code words formed using a non-binary, cyclic, error-correcting code. An offset word is additively superimposed on the code words to be transmitted, with a symbol of the alphabet being assigned to each symbol of the code word. In the receiver, the offset word is subtracted from the transmission signal and an error sample is generated by the generator polynomial underlying the code from the code word thus obtained, using polynomial division; the error sample is characteristic for the amount of deviation of the receiver's synchronization. Using a comparison of the error sample with all possible error samples, the exact amount of the synchronization deviation can be determined and thus the synchronization of the receiver can be restored.
The radio data system (RDS) is defined in DIN EN 50 067.
According to that reference, the information intended for the receiver is transmitted in groups. The individual groups are analyzed in different manners by the receiver. Each group consists of four blocks. One code word is transmitted in each block. Each code word consists of 26 bits, the first 16 bits of which are assigned to the information word and the following 10 bits are assigned to the check word. An additional offset word, also transmitted within the block and recognized as such in the receiver, is superimposed on each check word during transmission.
Depending on the group definition, either the same offset word (E) is superimposed on each block in the group or three offset words (A, B, D) used within a group form a cycle of four offset words with an additional variable offset word (C, C'). The cyclic use of offset words allows the transmitter to mark and the receiver to recognize the start of a group; when one of the cyclically used offset words is recognized in the receiver, its position in the group is also recognized. If the status of the block counter in the receiver matches this position at this time, the group clock that can be picked up at the block counter output is generated in the receiver synchronously with the transmitter. This allows the transmitted information words to be supplied to the analyzer.
When a receiver is turned on, or in the case of a switch-over to another transmitter or a longer shutdown of the transmitter, this match must be established for the first time or re-established, i.e., the receiver must be synchronized with the current transmitter. In Attachment C to the aforementioned DIN Standard EN 50 067, an embodiment of the block and group synchronization is explained for information. In the conventional embodiment for synchronization, the bits picked up at the output of the RDS receiver are supplied sequentially at the bit frequency to a 26-bit shift register. The stored bits are caused to cycle once in the shift register during each bit period and are received in a syndrome detection circuit, with an upstream register for polynomial division, for detection of the superimposed offset word. If the 26 bits stored in the shift register at a given time belong to the same block, a syndrome assigned to the offset word is detected in the circuit and a sync pulse can be picked up at the syndrome detection circuit output assigned to the recognized syndrome. This sync pulse is then analyzed in a control circuit, which, among other things, comprises a flywheel circuit.